master/slave flip-flop

A modern integrated-circuit flip-flop designed for high noise immunity. It is an advanced version of the versatile JK flip-flop, configured with two half-shift registers connected in tandem. The input half is the master, the output half the slave. A master-slave unit works on both edgesof the activating clock pulse. The information is loaded into the master on the leading edge, without effecting the outputs of the slave. When the data has stabilized, the trailing edge comes along to transfer it to the outputs of the slave. It is also known as a dual-rank JK flip-flop.; 一種現代的高抗噪 聲集成電路觸發器,是通用JK觸發器的改進型,由二只半移位寄存器級連而成。輸入半部 為主觸發器,輸出半部為從觸發器,主從觸發器由時鐘脈沖前后沿觸發而工作。信息在 脈沖前沿時進入主觸發器而不影響從觸發器的輸出;當數據已穩定時,脈沖后沿到來, 使其轉移至從觸發器。也稱為雙級JK觸發器。